1. Field of Invention
The invention relates to a system with an integrated packaging manufacturing method, and more particularly to a wafer level integrated packaging manufacturing method forming at least a passive component in the packaging structure to reduce the package volume and the system volume and decrease the signal degeneration due to the external connecting with passive components and breakdown problems.
2. Description of Related Arts
With the long time development, the IC packaging method can be categorized as pin through hole and surface mounting. The surface mounting method is processed to achieve an electric connecting through metal pads and substrate.
In a developing process for the surface mounting, there are some methods developed for an increasing of an integration of IC, such as the chip scale package (CSP) employed for the volume ratio of the naked die to the package less than 1:5. The CSP is achieved by fine pinch ball grid array or flip chip. There are many modified methods in the conventional flip chip packaging process. No matter what kind of modification, the flip chip packaging process employs the front surface of a wafer to achieve the electric connecting, such as the U.S. Pat. Nos. 5,720,100, 6,074,895, and 6,372,544. They all disclosed the flip chip structure as mentioned above. Therefore, those who employ the semiconductor structure of the front surface of a wafer, such as the photo sensor (CMOS or CCD structure), pressure sensor, or thermal sensor, cannot employ the flip chip packaging method.
Meanwhile, the wafer level chip scale package (WLCSP), which the volume ratio of the naked die to wafer is close to 1:1, is developed. WLCSP employs two surfaces and the lateral side of a wafer to process packaging so that the package volume can be reduced further.
An integrated method to integrate the passive components in the semiconductor packaging structure employing a semiconductor manufacturing process is developed to reduce the electronics system volume and decrease the signal degeneration due to the external connecting with passive components and the breakdown probability due to the malconnecting. But it needs the extra manufacturing process to form passive components. Not only the manufacturing process is complicated, but also does the breakdown problems of the manufacturing process increase.
Therefore, there is a need to provide an integrated packaging process and structure to integrate passive components in the packaging structure to reduce the system volume and increase the reliability through the integration of the passive components when processing the wafer level packaging.